It turns out with ESP32, the IO0 signal is read slightly earlier in the hardware bootstrapping sequence compared to ESP8266. The idea is to cancel out the scenario where both RTS & DTR are asserted by a serial terminal program, while still allowing the pins to be used individually for reset mode control. This "two transistors" circuit was first used on the NodeMCU development boards designed for the ESP8266 (I think by vowstar). This is possible, but it's not user friendly for dev boards aiming for ease of use. Asserting RTS holds the chip in reset indefinitely, so the serial program needs to be configured to disable hardware flow control signals. This has the problem that most serial terminal programs will (by default) assert both RTS & DTR when the serial port is opened.
This is still a valid option for low cost automatic boot mode circuits. Back in the day (2014?) some ESP8266 development boards wired RTS & DTR directly to EN & IO0. Mikemoy wrote:It seems like the transistor exclusive or network was legacy from some other chip that is not quite suited for the ESP32. I would really like to have a reliable USB serial flash connection, rather than the mystery. I am looking to make thousands of these boards for an internal IOT solution and would really like to solve this. This flaky operation seems to be a result of the circuit design of the two transistors which make the low state for IO0 or EN mutually exclusive. On 40 boards, about 2/3 work from the USB, the reset need me to manually assist with the flasher BOOT / EN buttons which are also on my board design. I have 5Kohm pull down on IO2 and a 12Kohm pull up on EN. I have build 40 boards with this circuit using the 12K ohm and S8050 transistors as called out. I think it works because there is a capacitor on EN which my hold it low long enough to get the IO0 pulse coincident. The circuit does not allow for both IO0 and EN to be low at the same time. This circuit does not allow for a DTR RTS combination which will pulse EN low while holding IO0 low. My understanding to enter serial flash upload mode, IO0 is held low, EN is pulsed low, then IO0 is brought high.
There is a logic table provided in the schematic I have build a board design with this exact circuit, as exampled in the dev kit schematics:
While both of my development boards work just fine, I believe the logic to this circuit has some real mysteries and is not reliable. I have searched and read all of the related internet posts regarding the ESP32 flashing mode which should be automatically entered using a usb serial interface on the development boards Rover and Dev Kit C.Įach of these boards employ a resistor / transistor bridge circuit from DTR and RTS to properly toggle the ESP32 EN and IO0.
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